module pwm_interface
(
input clk,
input rst_n,
input CS,
input wr_n,
input [7:0] addr,
input [31:0] data_wr,
output pwm_out0
);
reg [31:0] CCR0,CCR1;
reg en;
always @(posedge clk,negedge rst_n) begin 
	if(!rst_n) begin 
	end 
	else if((!wr_n)&&(CS))
	case (addr)
	8'd0: CCR0<=data_wr;
	8'd1: CCR1<=data_wr;
	8'd2: en<=data_wr[0];
	default : ;
	endcase 
	else begin 
	CCR0<=CCR0;
	CCR1<=CCR1;
	en<=en;
	end 
	
end 
Pwm_Core Pwm_Core_inst
(
	.clk(clk) ,	// input  clk_sig
	.rst_n(rst_n) ,	// input  rst_n_sig
	.CCR0(CCR0) ,	// input [31:0] CCR0_sig
	.CCR1(CCR1) ,	// input [31:0] CCR1_sig
	.en(en) ,	// input  en_sig
	.pwm_out(pwm_out0) 	// output  pwm_out_sig
);
endmodule 